embOS/IP Switch Board is intended to be mainly a demonstrator board for the Tail Tagging feature of SEGGER's embedded IP stack embOS/IP. Micrel/Microchip has developed switches which can expand one Ethernet port into 1+n fully independent ports, supported by the so-called Tail Tagging mode. This enhancement establishes a virtual Multiport when only one physical Ethernet port is available on the CPU - by choosing another PHY.
As core MCU an NXP Kinetis K66 is used. It is clocked at 180 MHz and comes with 256 KB SRAM as well as 2 MB Flash memory. Main peripheral functions used in this application are the USB2.0 controller with an integrated HS USB PHY and one Ethernet controller.
Quick and easy debug access to the Kinetis core MCU can be achieved by the J-Link OB, SEGGER's on-board debug probe.
The embOS/IP Switch board is powered by the USB device connector (B-type connector). Current consumption drawn depends on the configuration and connected Ethernet links. Idle consumption is approx. 140 mA. This USB interface can be used for a connection to a host providing High Speed USB2.0 device functionality (if provided by the application).